The present invention relates to a graphics overlay device, and more particularly to a graphics overlay device with improved overlaying speed.
Referring to FIG. 1, a conventional graphics overlay device includes a frame memory 4 for storing video data generated from a closed circuit digital (CCD) camera 1 and converted into a digital signal by an analog-to-digital (A/D) converter 2, a graphics overlay memory (GOM) 10 for storing graphics data, a look up table (LUT) 5 for outputting graphics overlay data obtained from overlaying the graphics data output from the GOM 10 and the digital video data output from the frame memory 4, a digital-to-analog (D/A) converter 6 for converting the graphics overlay data into corresponding analog data, a monitor 7 for displaying the analog video signal output from the D/A converter 6, a video address generator 8 for generating a video address signal which designates a location of the frame memory 4 (or GOM 10) which the digital video data (or graphics data) is to be stored in or read from, and a central processing unit 9 for generating the graphics data, a graphics address signal which designates a location of the GOM 10 on which the graphics data is to be stored and a select controlling signal which controls the storing and reading operations in the GOM 10. Here, the graphics data may be generated from the central processing unit 9 or provided from an external source. Moreover, the frame memory 4 may perform recording and reading operations at the same time using a dual port RAM.
Referring to FIG. 2, the GOM 10 includes a multiplexer (MUX) 12 for receiving the video address and the graphics address and outputting one of the two addresses according to a select controlling signal output from the central processing unit 9, a memory 14 which the graphics data is read from or written in according to the output address of the multiplexer 12, a graphics data buffer 16 for buffering and outputting the graphics data output from the memory 14 to the LUT 5, and a data buffer 18 between the memory 14 and the CPU 9 for buffering the graphics data.
The graphics overlay memory 10 operates as follows. If the select controlling signal (SELECT) output from the CPU 9 is HIGH, the multiplexer 12 outputs a video address transmitted from the video address generator 8 and the memory 14 outputs the data in the area designated by the graphics address to the graphics data buffer 16. The buffer 16 buffers the graphics data output from the memory 14 and then outputs the same to the LUT 5 shown in FIG. 1. The LUT 5 overlays the graphics data and the video data output from the frame memory 4. The graphics overlay video data output from the LUT 5 is converted into a corresponding analog video signal by the D/A converter 6 and displayed on the monitor 7.
If the select controlling signal (SELECT) output from the CPU 9 is LOW, the multiplexer 12 outputs a graphics address transmitted from the CPU 9 and the memory 14 stores the graphics data transmitted from the data buffer 18 in the location designated by the graphics address, thus renewing the contents of the memory 14.
FIG. 3 shows a horizontal sync signal for illustrating the read/write timing of the memory 14 shown in FIG. 2. The graphics data is read from the memory 14 during an effective scanning period A of the horizontal sync signal and recorded in the memory 14 during a horizontal blanking period B. Here, with the NTSC standard employed, the effective horizontal scanning period A is about 53 .mu.s and the horizontal blanking period B is about 10 .mu.s.
As shown in FIG. 3, because the graphics data is recorded in the memory 14 only during the horizontal blanking period B, a conventional graphics overlay device has a problem in that the graphics image flickers or the overlaying speed is lower when the graphics data is too large to be sufficiently recorded during the horizontal blanking period B.